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| CYIA2SC0300AA-BQE 1/3" VGA-Format CMOS Image Sensor Features * * * * * * VGA Resolution 1/3" Optical Format Automotive Grade device 120 db Dynamic Range 60 PIN CBGA Low power dissipation 1 Sensor Architecture Functional Description Cypress IM103 is Automotive grade CMOS Image Sensor with high dynamic range (120 db). IM103 is built with Autobrite(R) technology useful for Automotive Vision Systems which produce crisp clear video in visible and near IR wavelengths. Device can be used for Lane departure working, Night Vision, Adaptive Cruise control, driver drowsiness etc. The diagram in Figure 1 shows the major functional blocks of the imager. These blocks include: * Image sensor array * Row control circuitry * Column sense circuitry * Analog-to-digital converters * Timing and control logic * Program registers * Digital-output shift registers Sensor array: The sensor array consists of an optically active 482 row X 642 column matrix, with 18 additional dark columns on right side of the array (the array is described more fully in section 3). Each sensing element (pixel) is 8 m X 8 m in size. Timing and control circuitry: The sensor uses two clocks (data strobe or DSTR, and system clock or SCLK). Data strobe controls the timing of the output shift registers, while SCLK controls exposure and data conversion timing. Clocking details are given in section 5. Column circuitry: The column circuitry includes a column amplifier (with correlated double sampling [CDS] capability) and a 12-bit analog-to-digital converter (ADC). Multiple ADCs operate in parallel across the array. Output registers: Data from the ADCs are shifted into a parallel-in/serial-out 24-bit-wide row buffer. Data are shifted out to the parallel data I/O from the buffer after each row of data is converted. Introduction This document describes the automotive grade IM103 1/3" format VGA CMOS image sensor. The description covers: * Architecture * Operation * Wide-dynamic-range capture * Register settings * Electrical and electro-optical specifications This imager chip can be supplied in several different configurations including: * Monochrome or color pixel array Row Control Circuitry Sensor Array D0 D1 D2 D3 D4 D5 D6 D7 ROW SCLK Control Control Registers Logic Column Amplifiers/CDS Analog/Digital Converters Data Shift Registers RESET DSTR Figure 1. IM103 Image Sensor Block Diagram. Cypress Semiconductor Corporation Document #: 001-11358 Rev. ** * 198 Champion Court * WE OE San Jose, CA 95134-1709 * 408-943-2600 Revised October 13, 2006 CYIA2SC0300AA-BQE Control registers: Several on-chip programmable registers control exposure timing, digital gain, power, and dynamic range compression. These registers are described in more detail in section 7. 2 Pin Description The image sensor is packaged in a 60-pin CBGA. Only 41 of the 60 balls are active (Figure 2). These active pins are listed in Table 1, and include 8 digital I/O lines, 2 clock inputs, 8 power supply pins, 15 ground pins, 3 analog references, a row-synchronization output, a test I/O, an initialization input, and 2 control inputs. Pinout A B C D E F G H J 1 VDDIO D5 D4 GNDIO D3 D1 GNDIO NC 2 VDDIO GNDIO D7 D6 GNDIO D2 GNDIO GNDIO GNDIO 3 NC NC 4 NC NC 5 NC NC 6 NC NC 7 GPIO NC 8 VDDA GNDA 9 VDDA VDDA GNDA GNDA NC VDDD SCLK GNDD RESET 10 NC VREFP GNDA VREFM VCM VDDD VDDD GNDD NC GNDIO DSTR D0 NC NC ROW = NC = depopulated NC NC NC WE_N OE_N GNDD Figure 2. Pin Diagram for the IM103 VGA-format Image Sensor[1, 2] Table 1. IM103 Pin Assignments Pin A2,B1 C2 D2 C1 D1 F1 F2 G1 H4 J5 Name VDDIO D7 D6 D5 D4 D3 D2 D1 D0 ROW I/O Power Data I/O 7th bit (MSB) Data I/O 6th bit Data I/O 5th bit Data I/O 4th bit Data I/O 3rd bit Data I/O 2nd bit Data I/O 1st bit Data I/O 0th bit (LSB) Row Sync Out I/O Ground Data Strobe Clock Output Enable Write Enable Digital Ground System Clock Digital Power Sensor Reset/Initialization General-purpose I/O pin. Primarily used for testing Common-mode Voltage Capacitor Lower A/D Ref. Voltage Capacitor Function Class[3] P D D D D D D D D D P D D D P D P D D/A A A Type[4] PWR I/O I/O I/O I/O I/O I/O I/O I/O O GND I I I GND I PWR I I/O O O B2,E1,E2,G2,H1,H2,H3, J2 GNDIO J3 DSTR H8 J7 J8,H9,H10 G9 F9,F10,G10 J9 A7 E10 D10 OE_N WE_N GNDD SCLK VDDD RESET GPIO VCM VREFM Notes: 1. NC = No Connect. 2. The sensor is seen from the top (glass-lid) side in this view. 3. P = Power/Ground D = Digital A = Analog 4. PWR = Power Supply GND = Ground I/O = Bidirectional Input/Output I = Input O = Output Document #: 001-11358 Rev. ** Page 2 of 18 CYIA2SC0300AA-BQE Table 1. IM103 Pin Assignments(continued) Pin B8,C9,C10 B10 A8,A9,B9 Name GNDA VREFP VDDA Function Analog Ground Positive A/D Ref. Voltage Capacitor Analog Power Class[3] P A P Type[4] GND O PWR The major pin groups are described below: Digital I/O (D0-D7): These eight pins are bidirectional, tri-stateable digital I/O pins. The state of the pins is determined by WE and OE. In output mode, the eight pins are used to send image data out of the sensor to the system; in input mode, the eight pins are used to receive programming data for the on-chip registers. Write Enable and Output Enable (WE and OE): These two pins control the digital I/O pins. They determine whether the I/O pins are in programming, output, or high-impedance (tri-state) mode. Table 2 presents the I/O state as a function of WE and OE settings. Table 2. Data I/O Table WE HIGH LOW HIGH LOW OE HIGH HIGH LOW LOW Tri-state Input (write) enabled Output (data out) enabled Undefined Data I/O State GPIO: This pin is used primarily for test purposes during manufacturing. The pin can also be enabled with certain register settings to acquire data for noise correction. If the pin is not being used for noise correction, the recommended configuration is to tie it to ground through a 1-Mohm resistor. Analog Reference Pins (VREFM, VREFP, VCM): These pins are used to connect bypass capacitors for the three voltage references: negative reference (VREFM), positive reference (VREFP), and analog common-mode (VCM). The recommended bypass circuit is shown in Figure 3. The 3 analog references should be bypassed with at least 0.1-F ceramic capacitors. Cypress recommends the use of 0402-sized chip capacitors placed as close as possible to the package and sharing GNDA as the common node. VDDA VDDIO VREFP GNDA VREFM VCM Note: To minimize temporal noise the use of tri-state mode should be avoided during active operation of the image sensor. Either (a) active driving of the data bus or (b) use of pull-ups to define a known logic level is recommended during active operation. Tri-state mode can be used when the image sensor is in standby. RESET: This pin is used to initialize the sensor. It is normally HIGH during operation, and should be brought LOW for at least 100 s to initialize the sensor and set the default register values. The RESET signal also may be used as a chip enable. When RESET is LOW, the image sensor goes into sleep mode. Standby power in this situation is <0.5 mW. The sensor is brought out of sleep mode by setting RESET to HIGH. Data Strobe (DSTR) and System Clock (SCLK): These two clocks control the sensor. DSTR is used primarily to clock data out of the data shift registers. SCLK controls the row, frame, column circuit, and data conversion timings, as well as the program registers. The clocks can be asynchronous, but DSTR frequency must be at least 15X SCLK for 8-bit output format, and at least 22X SCLK for 12-bit output format. Clocking is described in more detail in section 5. Row Synchronization (ROW): This digital output pin provides a signal that goes HIGH at the end of each row readout. The signal goes LOW at the start of the next row. VDDD Figure 3. Bypass capacitor circuit for VREFM, VREFP, VCM, VDDIO and VDDA. Recommended bypass capacitor value is 0.1 F. Supply pins (VDDD, VDDIO, VDDA): These three pins separately supply power for digital circuitry (VDDD), I/O (VDDIO), and analog circuitry (VDDA). The supplies are run on separate busses on the chip but are connected through ESD blocking diodes. Because of the ESD protection diodes, the three voltages should be kept at the same value. Grounds (GNDD, GNDIO, GNDA): These three pins separately supply grounds for digital circuitry (GNDD), I/O (GNDIO), and analog circuitry (GNDA). The grounds run separately in metal, but are tied together through the silicon substrate in the circuit. Document #: 001-11358 Rev. ** Page 3 of 18 CYIA2SC0300AA-BQE 3 Imager Array Description Die photograph: A photograph of the IM103 die is shown in Figure 4. Major features of interest include: * Row control circuitry (to the left of the array as shown). * Column amplifiers/correlated double sample circuits and analog-to-digital converters, arranged above and below the image sensor array. * Data registers (arranged above/below the analog-to-digital converters). Image Array "Frame": A schematic representation of the array is shown in Figure 5. Row drivers: As noted above, the row circuitry is located on the left side of the array. This circuitry controls various row-related signals (including the reset signal, the row select signal, and the hard/soft reset signal). Timing for the row drivers is controlled by SCLK. Column circuitry/ADCs: The column amplifiers/CDS circuits and analog-to-digital converters are located above and below the sensor array. Each column has its own amplifier/CDS circuit, while each ADC is shared between two columns. Timing for column sampling and analog-to-digital conversion is controlled by SCLK. The location of the column amplifiers and ADCs alternates between the top and bottom of the array, according to which pair of columns is being read out. Columns 0, 1, 4, 5, ..., 4n, 4n+1 use amplifiers and ADCs at the bottom of the array, while columns 2, 3, 6, 7, ..., 4n+2, 4n+3 use amplifiers and ADCs at the top of the array. Figure 4. IM103 Die Photograph Showing the Physical Location of Major Functional Blocks ........ ADC ........ TO PIN 1 MUX CDS/AMP ) COL 642 (DARK ) COL 643 (DARK COL 638 COL 639 COL 640 COL 641 COL 0 COL 1 COL 2 COL 3 ROW 481 ROW 480 ROW 479 ROW 478 ........ ... ... ... ... ... ... ........ ... ....... ... ... ... ... ... ... ... Sensor Array ROW 3 ROW 2 ROW 1 ROW 0 ........ CDS/AMP ........ ... ....... CDS/AMP MUX ADC Input from register 0 MUX ADC Figure 5. Imager Frame, showing the row control shift register (to the left) and the column amplifiers/MUXes/ADCs (top and bottom) Document #: 001-11358 Rev. ** Page 4 of 18 COL 659 (DARK) ... CYIA2SC0300AA-BQE Data registers: Each ADC is followed by a 24-bit-deep data register which is read in serially. Data from the even columns (0, 2, 4 ...) is read in first from MSB to LSB, followed by data from the odd columns, again from MSB to LSB (Figure 6). The read-in timing is derived from SCLK. C o l. I C o l. I+ 1 Data are shifted out in parallel and then interleaved at the end of the register array to properly sequence odd and even column data from the top and bottom of the array. Data readout timing is controlled by DSTR. Image Array: The image array (Figure 7) contains 482 optically active (light-sensitive) rows and 642 optically-active columns. In addition, 2 "dark" columns are provided on one side of the array. The array is addressed as shown in Figure 7. When package pin 1 is above the array, the dark columns are to the right of the array. Row addressing starts at the bottom of the array, and columns are read out from left to right. Using this arrangement, the first pixel to be read out during an exposure is at the bottom left of the array, while the last pixel to be read is at the top right. C D S /C o lu m n A m p s A n a lo g M U X 1 2 -b it R e c u r s iv e A D C LSB C o l. I+ 1 MSB LSB C o l. I MSB Figure 6. Data Read-in Sequence for the Data Register Document #: 001-11358 Rev. ** Page 5 of 18 CYIA2SC0300AA-BQE 638 639 640 641 0 1 2 3 C OLUM N C OLUM N C OLUM N C OLUM N ........ TO PIN 1 ........ C OLUM N 642 (D AR K) C OLUM N 643 (D AR K) ........ ........ ........ ........ .... ........ Sensor Array ........ ........ ........ ROW 3 ROW 2 ROW 1 ROW 0 ........ ........ .... Figure 7. Image Sensor pixel array layout and color filter arrangement on pixel array. The first pixel to be read is a RED pixel. Package pin 1 is to the top, and the Data I/O pins are to the left in this drawing. NOTE: In a camera application, package pin 1 would be oriented toward the top of the subject, to account for the inverting nature of the optics. Document #: 001-11358 Rev. ** Page 6 of 18 C OLUM N 659 (D AR K) ROW 481 ROW 480 ROW 479 ROW 478 C OLUM N CO LUM N C OLUM N CO LUM N CYIA2SC0300AA-BQE 4 Pixel Description and Operation Pixel Design: The IM103 uses a three-transistor pixel built around an n-well photodiode (Figure 8). The pixel is connected by 2 power lines, 2 control lines, and an output line. The pixel has two operational sections: (1) a sensing section consisting of the reset MOS gate and the n-well photodiode, and (2) a readout section consisting of an MOS source-follower transistor and a row select gate. The potential of the n-well photodiode can be controlled by applying appropriate signals to the reset MOS gate and the reset Vdd line. These signals are used to reset the photodiode potential to a reference value for the start of integration, and also for wide-dynamic-range operation. The source-follower gate provides a buffer between the relatively small capacitance associated with the photodiode node and the much larger capacitance on the column line. Row Select is used to connect all pixel source followers on a given row to the column line for readout. Pixel Operation in Linear Mode: Pixel operation in linear mode consists of the following steps: * The pixel is reset by applying Vdd to the reset gate. This operation brings the photodiode potential to a value near Vdd. * After reset, photons entering the silicon are converted to photoelectrons and collected on the positively charged photodiode node. As electrons accumulate on the photodiode, the potential of the photodiode relaxes towards ground. * After a predetermined period (the "integration time", Tint), Row Select is pulsed high and the output transferred onto the column line and sampled by the column amplifier. Row Select is then brought low. * The pixel is reset, Row Select is pulsed high a second time, and the reset level transferred onto the column line and sampled by the column amplifier. This second readout (a "correlated double sample" or CDS) generates a self-referenced differential signal that eliminates several systematic errors due to device and layout mismatches. The number of photoelectrons collected by the photodiode is proportional to the intensity of the light hitting the pixel. The well capacitance varies slowly with potential, so that the output voltage change is approximately linear with respect to the number of electrons collected on the photodiode. Vdd Reset Vdd Barrier (Reset) Row Select A sketch of the time dependence of the pixel voltage is shown for several illumination levels in Figure 9. The corresponding output signals are also shown. Output (to CDS/ADC) Figure 8. Three-transistor Pixel Design used in the IM103 Sensor Array Document #: 001-11358 Rev. ** Page 7 of 18 CYIA2SC0300AA-BQE Integration period Light Intensity Pixel Voltages Pixel Output Time Reset Voltage Photodiode Voltage Illumination Figure 9. Left: Sketch of photodiode pixel voltage vs. time showing how different light intensities affect this parameter. Right: Sketch of the corresponding sensor ADC output vs illumination. The response is linear with an eventual saturation. Pixel Operation in Wide-dynamic-range Mode: The pixel response can be made nonlinear by applying Cypress's proprietary variable height multiple reset method (Autobrite(R)). The row control circuitry provides 8 variable reset levels (b0 through b7), where b0 is Vdda = reset level, b7 is ground, and b1 through b6 are intermediate levels. Pixel response characteristics can be modified by changing the variable reset voltages and their timing. More details on implementing wide-dynamic-range operation can be obtained by contacting Cypress. There are 48 SCLK periods per row, as shown in Figure 11. For 60-fps operation, the circuit requires SCLK to be approximately 1.5 MHz. SCLK is not required to have a 50% duty ratio. The pulse width may be very small compared to the clock period, but the minimum pulse width is 20 ns. Row Synchronization: The only output from the image sensor besides the data bus is the ROW signal. The ROW signal stays HIGH for one SCLK period during a row time. When ROW goes HIGH, the system must stop reading data from the sensor. The period when ROW is HIGH is a good time to write data to the image sensor program registers (Figure 14). When ROW falls, the most recently converted row of pixels may be read out of the row buffers by the system. The system may read out the data at any rate as long as readout is finished before the next ROW pulse (Figure 12). More restrictive data readout conditions that reduce temporal row noise are described below. 5 Interfacing to the IM103 Clock Requirements: The imager requires a steady system clock (SCLK) signal. SCLK sets the row rate, which in turn determines the frame rate. Figure 10 illustrates the relationship between DSTR and SCLK. Figure 10. Relationship between DSTR and SCLK NOTE: The relationship between DSTR and SCLK depends on output-data format. For 12-bit format, fDSTR must be at least 22 X fSCLK. For 8-bit format, fDSTR must be at least 15 X fSCLK, as shown. Document #: 001-11358 Rev. ** Page 8 of 18 CYIA2SC0300AA-BQE Figure 11. Row Timing Diagram There are 48 SCLK cycles in each row period. Figure 12. Data Readout Timing Data is read out while ROW is low and OE is low. Data is ready for readout after the falling edge of ROW. All data must be read out before the rising edge of the next ROW signal. One 8-bit word is read out per DSTR clock cycle. 12-bit/pixel data format requires 3 DSTR clock cycles to read 2 pixels, while 8-bit/pixel data format requires 1 DSTR clock cycle/pixel. D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 P l 0 (1 ) ixe 1 P l 0 (1 ) ixe 0 P l 0 (9 ixe ) P l 0 (8 ixe ) P l 0 (7 ixe ) P l 0 (6 ixe ) P l 0 (5 ixe ) P l 0 (4 ixe ) st L C 1 CO K C CE YL P l 0 (3 ixe ) P l 0 (2 ixe ) P l 0 (1 ixe ) P l 0 (0 ixe ) P l 1 (1 ) ixe 1 P l 1 (1 ) ixe 0 P l 1 (9 ixe ) P l 1 (8 ixe ) n 2d C O K LC C CE YL P l 1 (7 ixe ) P l 1 (6 ixe ) P l 1 (5 ixe ) P l 1 (4 ixe ) P l 1 (3 ixe ) P l 1 (2 ixe ) P l 1 (1 ixe ) P l 1 (0 ixe ) rd L C 3 CO K C CE YL D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 P l 0 (7 ixe ) P l 0 (6 ixe ) P l 0 (5 ixe ) P l 0 (4 ixe ) P l 0 (3 ixe ) P l 0 (2 ixe ) P l 0 (1 ixe ) P l 0 (0 ixe ) st L C 1 CO K C CE YL P l 1 (7 ixe ) P l 1 (6 ixe ) P l 1 (5 ixe ) P l 1 (4 ixe ) P l 1 (3 ixe ) P l 1 (2 ixe ) P l 1 (1 ixe ) P l 1 (0 ixe ) n 2d C O K LC C CE YL P l 2 (7 ixe ) P l 2 (6 ixe ) P l 2 (5 ixe ) P l 2 (4 ixe ) P l 2 (3 ixe ) P l 2 (2 ixe ) P l 2 (1 ixe ) P l 2 (0 ixe ) rd L C 3 CO K C CE YL (a) (b) Figure 13. Data Output Format Sequence for (a) 12-bit and (b) 8-bit output-format modes Document #: 001-11358 Rev. ** Page 9 of 18 CYIA2SC0300AA-BQE Figure 14. Timing for Writing Data to the On-board Registers through the Data Bus. Data may be written to the sensor at any time. Data is updated to the registers on the falling edge of ROW. Data Readout: Data can be read out in different ways. DSTR is used to clock out the data, and it can be a constant clock signal or a strobe. If DSTR is a constant clock, the data is advanced only when OE is brought LOW. If the strobe approach is used, OE should be brought LOW first and then the system can strobe the data. When OE is brought HIGH, other devices like SRAM or FLASH may be active on the bus. OE should be synchronous to DSTR if the continuous clock method is used. The format of the data is raster. The first valid byte of a row occurs after the rising edge of DSTR. The data output format (12-bit or 8-bit, as set by the user) significantly affects the data stream, as follows (Figure 13): In 12-bit data format mode, pixel data are separated and streamed as 8-bit words. Therefore, 3 cycles of DSTR are required to read out 2 pixels. In 12-bit mode, the first clock cycle reads out the 8 most significant bits of the 1st pixel. The second clock cycle reads out the 4 least significant bits from the 1st pixel as the upper 4 bits of the output, and the 4 most significant bits of the 2nd pixel as the lower 4 bits of the output. On the 3rd cycle, the 8 least significant bits of the 2nd pixel are read out. The sequence repeats on the 4th cycle. In 8-bit mode, the data come off the bus sequentially as complete pixel words. Clocking conditions for low temporal noise: Twice during the row period, the image sensor samples the pixel voltage levels of the row being read out. The sensor is most sensitive to noise during these sampling periods. In particular, readout of the data buffers may introduce noise into the circuit and disturb the sensor voltage levels. Such noise usually appears as temporal row noise (i.e., random horizontal line flicker from frame to frame). To minimize this noise, it is recommended that DSTR be gated so that data readout is avoided during the sampling periods. The sclk periods when sampling occurs are 28-29 and 45 after a row goes high (out of 48 sclk periods). 6 Programming the IM103 The IM103 image sensor has 12 on-board 4-bit programmable registers for controlling its operation. All configuration of the imager is performed over the data bus. To set power, gain, data format, or other functions, the controller/host must write the appropriate words to the program registers. In order to write data, the data bus pins first must be set to input mode. This is accomplished by setting output enable (OE) high. The programmable registers are updated when the write enable (WE) input signal goes low. Data on the data bus must be set up before WE is brought low and be held for a short time after WE is brought high (Figure 14). The 8-bit word written to the data I/O lines contains 4 bits of address (the upper 4 bits, ADR(3)-ADR(0)) and 4 bits of program data (the lower 4 bits, P(3)-P(0)) (Figure 15). A A AA P PP P DR(D( R ( D R3 ( (DR( 3 2 1 0 ) 2( ) ) ) ) ) 1( )0 ) Figure 15. Configuration of the 8-bit Words used to Program the IM-103 On-board Registers Document #: 001-11358 Rev. ** Page 10 of 18 CYIA2SC0300AA-BQE 7 Register Descriptions NOTE: Reserved registers should not be programmed differently from the recommended values. If a reserved register is accidentally programmed differently, the sensor should be reinitialized using the RESET signal. General descriptions of the 12 on-board registers are listed in Table 3. Detailed descriptions of the register bit functions are given in Tables Table 4 through Table 15. NOTE: The on-board registers are set to the default values in Table 3 through Table 15 after a RESET signal. Table 3.IM103 On-chip Registers Register 0 1 2 3 4 5 6 7 8 9 10 11 Function Frame start and dynamic range compression Noise reduction and reset control signals Noise reduction control signals Noise reduction control signals Reset level, clamp, and test pin analog modes GPIO pin modes Reverse saturation control modes Data output format and gain settings Power setting Power management Variable reset level test and control Dynamic range compression control Default Value 6 7 2 3 8 0 1 0 2 F 1 8 Recommended Value 7 (hard reset) or 3 (soft reset) A F (hard reset) or E (soft reset) 8 0 (active pixel) or 8 (ADC test) 2 4 D 0 or 8 depending on desired compression 0 Register 0: This register (Table 4) manages the start of frame and variable reset levels. Table 4.Register 0 Description Bit 0 1 2 3 b<0> b<1> b<2> rs Name Default 0 1 1 0 Function LSB of pixel reset/compression control 2nd bit of pixel reset/compression control MSB of pixel reset/compression control Starts frame capture (synchronous) next transition of ROW. A conventional linear image capture (i.e., no dynamic range compression) is programmed by writing 00001000 (x08) followed by 00000111 (x07) to the program register. Autobrite(R) compressed images are programmed by writing additional words to register 0 after 00000111 (x07). (See the examples at the end of this section for more details.) Note: A new frame can also be started by applying a RESET signal. The difference between a register 0 frame start and a RESET frame start is that the register 0 frame start is synchronous. Use of the register 0 approach maintains a consistent integration interval from frame to frame. b<0>, b<1>, b<2>: These bits determine the variable reset magnitude. Since there are 3 of these bits, 8 different levels are possible. b<0:2> = 000 corresponds to the highest variable reset value (Vdd for reset), and b<0:2> = 111 corresponds to the lowest value (ground). Fine tuning of the voltages that correspond to the variable reset heights can be done with other registers (described below). rs: This bit is used to start a new frame. The system initiates a frame by writing a `1' to bit 3 with the pixel reset value in bits 0-2. The 8-bit word is therefore: 00001000 (x08). When ROW (output) falls, the frame starts. Whenever a `1' is written to bit 3, a `0' must be written on the Document #: 001-11358 Rev. ** Page 11 of 18 CYIA2SC0300AA-BQE Register 1: This register (Table 5) controls noise cancellation circuitry for pixel-reset/row-select signals and enables hard reset operation. Table 5.Register 1 Description Bit 0 1 2 3 enfreset enrdrop envdrop reserved Name Default 1 1 1 0 Function When HIGH: Enables pixel reset signal noise reduction When HIGH: Enables row select signal noise reduction When HIGH: Enables hard reset operation Bit must be kept LOW A "soft" reset occurs when the reset transistor is operated in sub-threshold on pixel reset. Under these conditions the reset noise is ~ kT2 . C Provided pixel reset noise is a considerable noise source, this discussion suggests that "soft" reset operation has significantly less noise than "hard" reset operation. In the IM103 imager, the dark temporal noise is typically ~3LSB (12-bit) in "soft" reset mode and ~4.5LSB (12-bit) in "hard" reset mode (25 fps, T=33 full-frame integration). C, "Soft" reset mode has more image lag than "hard" reset mode. Lag occurs when the reset value of a pixel is dependent on its previous value. Because there is a limited settling time and the reset transistor is never driven above threshold, lag is more prevalent in "soft" reset mode. A trade-off between less noise or less image lag must therefore be made when deciding whether to use "soft" or "hard" reset mode. ENFRESET and ENRDROP: Bits 0 and 1 enable noise reduction circuitry essential to effective operation of the imager. Both of these bits should be set equal to 1 at all times. ENVDROP: Bit 2 on register 1 controls how the pixels are reset. The voltage level to which a pixel settles after being reset (Vo) can vary both spatially and temporally. Some of this variability arises from pixel-to-pixel differences in transistor thresholds etc. which contributes to fixed pattern noise. There is also a random component to Vo originating ultimately from thermal noise. This noise component is commonly referred to as (kT/C) or reset noise. Reset noise depends on how the reset transistor is operated. A "hard" reset occurs when this transistor is driven above threshold on pixel reset. Under these conditions it can be shown that the thermal noise associated with pixel reset is proportional to kTC where C is the sense node capacitance, k is Boltzmann's constant, and T is the temperature in degrees Kelvin. Register 2: This register (Table 6) enables various noise reduction and reset modes. Table 6.Register 2 Description Bit 0 1 2 3 reserved reserved reserved enshort Name Default 0 1 0 0 Bit must be kept LOW. Bit must be kept HIGH. Bit must be kept LOW. When HIGH: Enables circuitry to minimize column noise. sen (register 9, bit 1) should be set low when enshort is set high. Function ENSHORT: Enshort enables circuitry that minimizes column line noise. Register 3: This register (Table 7) enables various noise reduction and reset features. Table 7.Register 3 Description Bit 0 1 2 3 Name enrdropdrop encdsload reserved reserved Default 1 1 0 0 Function When HIGH: Enables hard reset noise reduction circuitry. When HIGH: Reduces CDS amplifier noise. Bit must be kept HIGH. Bit must be kept HIGH. ENCDSLOAD This register reduces noise in the column circuit prior to the ADCs. Typically, 1dB of noise reduction will occur in low light illumination when this bit is set high. ENRDROPDROP: This bit enables noise reduction circuitry used in hard reset mode. It should be set high whenever the imager is operated in hard reset mode, and low in soft reset mode. Document #: 001-11358 Rev. ** Page 12 of 18 CYIA2SC0300AA-BQE Register 4: This register (Table 8) controls the GPIO pin output and enables a feature that minimizes reverse saturation of the pixel signals. Table 8. Register 4 Description Bit 0 1 2 3 a<0> a<1> a<2> enclamp Name Default 0 0 0 1 Function Hard reset level bit OR analog test selection bit 0 (see text) Hard reset level bit OR analog test selection bit 1 (see text) Hard reset level bit OR analog test selection bit 2 (see text) When HIGH: Enables circuitry that minimizes "reverse" saturation effects. When aten (register 5, bit 0) is high, a<0:2> selects analog voltages for test purposes. ENCLAMP: This register enables circuitry that prevents "reverse saturation" of pixel signals under high illumination. This register should be set high during normal imager operation. a<0>, a<1>, a<2>: These registers are used for two separate functions. When aten (register 5, bit 0) = 0 and envdrop = 1, a<0:2> select how far above threshold the reset transistor is driven during hard reset. For this function the recommended setting is a<0:2> = 000. Register 5: This register (Table 9) controls the GPIO pin output and enables ADC test mode. Table 9.Register 5 Description Bit 0 1 2 3 aten reserved reserved vten Name Default 0 0 0 0 Bit must be kept LOW. Bit must be kept LOW. When HIGH: Enables voltage input on GPIO pin for testing ADC and CDS circuits. Also very useful in minimizing column fixed pattern noise. mismatches between the ADCs can be corrected by operating the imager in this mode, saving the resulting column means, and subsequently correcting image data. Function When HIGH: Enables analog voltage test output on GPIO pin. ATEN: This register enables the GPIO pin for analog output. VTEN: ADC test mode is enabled by setting vten = 1. In this mode a voltage signal can be sent to the CDS/ADC block through the GPIO pin. Column fixed pattern noise arising from Register 6: This register (Table 10) is currently not in use. Bits on this register should not be changed from their default settings. Table 10.Register 6 Description Bit 0 1 2 3 reserved reserved reserved reserved Name Default 0 0 1 0 Clamp Level Control Clamp Level Control Clamp Level Control Clamp Level Control Function Register 7: This register (Table 11) controls the data format (12 bit or 8 bit) and gain (for 8-bit format only). Table 11.Register 7 Description Bit 0 1 2 3 g(0) g(1) g(2) fmode Name Default 0 0 0 0 Gain bit 0 Gain bit 1 Gain bit 2 When HIGH: Output is in 12-bit mode. When LOW: Output is in 8-bit mode and gain is enabled. where G is the 3-bit number determined from register 7, bits 0-2. The maximum gain is 16X, or G = 100. Valid settings for G are 000, 001, 010, 011, and 100, for GAIN = 1, 2, 4, 8, and 16X, respectively. Function FMODE: When fmode (bit 3) is HIGH, data is output from the sensor at 12 bits/pixel. When fmode is LOW, data is output at 8 bits/pixel, and digital gain is enabled. g<0>, g<1>, and g<2>: Gain can be set from 1X to 16X in powers of 2. The gain is given by: GAIN = 2G Document #: 001-11358 Rev. ** Page 13 of 18 CYIA2SC0300AA-BQE Register 8: This register (Table 12) controls the analog power on the sensor by setting the analog currents. Table 12.Register 8 Description Bit 0 1 2 3 p(0) p(1) p(2) p(3) Name Default 0 1 0 0 LSB of power setting. 2nd bit of power setting. 3rd bit of power setting. MSB of power setting. (x8F). A minimum power setting of 4 (p<0:3> = 100) is recommended. NOTE: Although analog power dissipation is a major component of total power dissipation, other factors such as frame rate influence the total device power dissipation. Function p<0>, p<1>, p<2>: The analog current is related to the register 8 setting by the following (approximate) relation: Analog Current = 0.5 mA + (CurrSet)*1.25 mA where CurrSet is the 4-bit number programmed into register 8. The minimum analog current is approximately 0.5 mA, at (x80). The maximum analog current is approximately 19.25 mA, at Register 9: This register (Table 13) controls the state of various internal analog current sources. Table 13.Register 9 Description Bit 0 1 2 3 bgen sen adcen cdsen Name Default 1 1 1 1 Function When HIGH: Bandgap reference current source is enabled. When LOW, bandgap reference is disabled (imager will not function) When HIGH, column source-follower current source is enabled. When LOW, column source-follower current source is disabled. When HIGH, analog/digital converter is enabled. When LOW, analog/digital converter is disabled (imager will not function). When HIGH, column amplifier is enabled. When LOW, column amplifier is disabled (imager will not function). SEN: Column line current sources are activated when sen = 1. When enshort = 1, sen should be set LOW BGEN, ADCEN, AND CDSEN: These bits enable various analog current source circuits that are essential to the operation of the imager. They should only be disabled to conserve power when the imager is in stand-by mode. Register 10: This register (Table 14) is used for test purposes and control of variable reset voltage levels. Table 14.Register 10 Description Bit 0 1 2 3 reserved reserved reserved b1sel Name Default 1 0 0 0 reserved reserved reserved Shifts variable reset voltage levels Function B1SEL This bit changes the voltage level of variable reset levels 1-6. Enabling b1sel reduces the overall amount of compression in Autobrite mode. Register 11: This register (Table 15) controls dynamic range compression when digital gain is used. Table 15.Register 11 Description Bit 0 1 2 3 squ<0> squ<1> squ<2> autosquash Name Default 0 0 0 1 Function LSB for manual gain compensation. 2nd bit for manual gain compensation. MSB for manual gain compensation. When HIGH: Enables automatic gain compensation. When LOW: Enables manual gain compensation. greater, pixels will saturate an 8-bit scale at lower illumination levels than 1X gain mode. This in turn will progressively make the least compressive variable reset levels ineffective. To Page 14 of 18 squ<0>, squ<1>, squ<2>: These bits adjust the variable reset levels to compensate for any gain that is applied when operating in 8-bit mode (fmode=0). When the gain is 2X or Document #: 001-11358 Rev. ** CYIA2SC0300AA-BQE compensate for this effect, the variable reset levels can be shifted by enabling these bits. To perform this procedure manually, the autosquash bit must be set to 0. Note: Setting squ<0:2> to values higher than 100 will produce variable reset levels equivalent to squ<0:2> = 100. AUTOSQUASH: When this bit is set to 0 the variable reset levels can be adjusted manually with squ<2:0>. When it is set to 1 the variable reset levels are adjusted by the gain settings on register 7, g<0:2>. Table 16.Example Programming for Shutter Speed Equal to 1/2 Frame Rate Rowcount 0 1 255 256 0 (next frame) Databus x08 x07 x00 x07 x08 8 Example: Programming the IM103 for Linear-mode Image Capture The following example describes how to program the IM103 to capture images in the conventional linear mode. In this mode pixel output is linearly proportional to input illumination; no on-chip dynamic range compression is used. There are 482 active rows in the sensor. Once a frame has started, at least 482 ROW signals must pass before a new frame is started. A convenient approach is to let the frame contain 512 (29) ROW signals. Such a frame will contain 30 blank rows. These 30 extra row times can be used as a vertical blanking period or as a time to calculate the next exposure and process data. When capturing an image, the controller should keep track of the row count. At row count 0, the start of frame instruction is written to the sensor. This is done by writing x08 over the data bus. At row count 1, the controller must write a new value to address x0 to turn off the frame start signal. This can be done by writing x07 or another value depending on the exposure time. When ready to integrate, the controller writes x00 to the sensor followed by x07. The integration (or exposure) time is determined by the number of row periods remaining in the frame after the integration signal is written (see Figure 16): Tint = ((Rows - IntStart)/Rows) * 1/FrameRate where: Rows = total rows in frame (including virtual rows). IntStart = the number of rows that pass before writing the integration word to the sensor. FrameRate = sclk/(Rows)/48. To set exposure, the system controller determines the appropriate exposure time and tells the imager to start integrating at IntStart. For example, if a shutter speed equal to half of the frame rate is desired, the following sequence of words would be written to the sensor: The following tables give additional examples of exposure control: Table 17.Example Programming for Shutter Speed Equal to 511/512 Frame Rate Rowcount 0 1 0 (next frame) Databus x08 x07 x08 Note 511/512 frametime Table 18.Example Programming for Shutter Speed Equal to 384/512 Frame Rate Rowcount 0 1 128 129 0 (next frame) Databus x08 x07 x00 x07 x08 Note 384/512 frametime Table 19.Example Programming for Shutter Speed Equal to 1/512 Frame Rate Rowcount 0 1 510 511 0 (next frame) Databus x08 x07 x00 x07 x08 Note 1/512 frametime When exposure is set to full integration and more brightness is required, gain may be used in 8-bit mode (by setting register 7). The system controller would then need to control both gain and integration. Document #: 001-11358 Rev. ** Page 15 of 18 CYIA2SC0300AA-BQE Figure 16. Timing of Program Register Instructions for Linear-response Mode The sensor is initially programmed to x08 at RowCount = 0 (setting start of frame). At RowCount = 1 (next ROW pulse), x07 is written to the sensor. At RowCount = n (equivalent to IntStart in the text) integration is initiated by writing x00 followed by x07 at RowCount = n+1. The sequence repeats at the start of the next frame. 9 Schematic of the Package The schematic of the package of the imager is as shown below. 60 Lead, Custom CBGA Section AA 1 9 .525 0.1 0.5 0.05 1 8 0.1 "T" 0.5 0.025 5.7 A IM103-A(~F) (6.718, 6.3179) SMaL Camera Die Center Package and Optical Center A 1 Top View 1 2.5 0.3 10 9.5 7.5 5 0.1 1.4 1 0.3 0.066 Offset in mm SMaL Camera (0, 0) JWY 0.5 layer 4 layer 3 layers 1 & 2 2.28 8.26 5 0.1 9.66 5 0.1 1 A Glass Lid 0.26 0.76 0.75 Target tolerance on pad dia =0.05mm Dimensions: mm Package Die "D" Document #: 001-11358 Rev. ** Page 16 of 18 1 J 8.5 9.5 0 0.1 .5 O0 CYIA2SC0300AA-BQE 10 Optical Window 2. Protects the wire bonds c. Option is provide die in wafer form Question: What are the recommendations to handle the image without the optical window Answer: Standard practise for packaging image sensors is to singulate the wafer and immediately package the sensors into a package or camera module within a class 100 or better clean room. Extreme care and appropriate processing is required to "seal" the optical path within 0.5mm of the image plane so that particle does not create dark defects in the image. Question: Could the imager qualification be compromised from the optical removal window? Answer: a. Yes, Silicon sensor reliability in the field depends on how it is packaged. Cypress has not qualified an open package for the reasons stated above. The options are: i. Buy the sensor in a qualified package. ii. Buy sensor in die from (generally wafer) in which case the customer receives qualified silicon but customer must manage the reliability of the sensor in their package or system Question: What is the thickness (T) of the optical window? Answer: The optical window thickness (T) is 0.5mm thick. Question: What is the distance (D) between the upper surface of the die and lower (internal) surface of the optical window? Answer: The distance (D) between the upper surface of the die and the lower (internal) surface of the optical window is 0.26 mm and this includes a 0.03 mm bond line. Question: Depending on the former dimensions (if T+D>0.4_0.5 mm): would it be possible to have the imager without the optical window in our development phase (and in more general during the production phase)? Answer: a) Total distance between the image plane (top of sensor) and the top of the glass is 0.76 mm. b) No. i) The window provides two critical functions 1. Protects the optical path from particles that will be imaged Autobrite is a registered trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-11358 Rev. ** Page 17 of 18 (c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CYIA2SC0300AA-BQE Document History Page Document Title: 1/3" VGA-Format CMOS Image Sensor Document Number: 001-11358 REV. ** ECN NO. 503768 Issue Date See ECN Orig. of Change QGS Description of Change New Datasheet Document #: 001-11358 Rev. ** Page 18 of 18 |
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